As employed in the fabrication of semiconductor wafers, photolithographic processes involve the use of a mask to define desired circuit patterns. The mask is precisely aligned with a wafer, or with a pattern previously formed on the wafer. In order to ensure proper placement and dimensions of the image, a pattern of alignment marks is included in the mask design, and it is typically placed in the scribe streets between the individual chips, so as to avoid encroachment into the space used for active circuitry. “Alignment mark” is a term referring to a set of defined geometric shapes or images.
As the number of individual circuits on an integrated circuit has increased, and the feature sizes have shrunk, multiple layers of insulating and conducting materials have been formed and patterned by successive imaging steps. The precise registry of successive images in such multiple layers is extremely critical. Typically a precision alignment system is used to measure relative feature positions so that the current level is exposed in the correct position relative to the prior level.
Numerous alignment marks having a variety of sizes and shapes have been used in the industry to insure precise placement of the various levels in VLSI (very large scale integration) device fabrication, but those conventional alignment marks are not adequate in the context of this invention. Instead, this invention is concerned with a new type of alignment mark to be used in conjunction with e-beam imaging to identify specific locations on a chip.
As progressive shrinking of integrated circuits to submicron-sized features has developed, identifying and eliminating defects formed during wafer processing has become increasingly more important, and also more difficult. Previously used optical inspection of the devices is ineffective, laborious, and costly.
Fast response, high magnification inspection techniques are required to support rapid defect learning and to ensure device reliability, particularly during the product development phase. Automated e-beam wafer imaging tools with high resolution and large depth-of-focus have been developed in response to the need for rapid feedback on process or reticle defects which cannot be observed by conventional optical inspection. In general the imaging tools operate by rastering an e-beam across a wafer, and comparing the signal from a given position on chips to the same position on two adjacent chips.
An example of such inspection equipment is SEMSpec or ES20 from KLA-Tencor in San Jose, Calif. The automated inspection tools can operate in various modes, such as SEM (scanning electron microscopy) for inspection of physical defects, or in voltage contrast mode which detects abnormal voltage contrast levels.
Complete fabrication of a complex device often takes approximately 30 to 75 days; therefore it is important that defects be caught as early as possible during wafer processing in order to correct mask or reticle defects and/or process problems. Detection and correction of a defect early in the wafer processing cycle, rather than by circuit testing and failure analysis of the finished device can save significantly in product development costs and time.
E-beam inspection can shorten response time from 1 to 2 months for functional testing of a finished device, to 1 to 2 days for state-of-the-art e-beam inspection. (J. Garvin, M. Tinker, N. Sridhar, R. Guldi, R. Chappel, T. Cass and K. Roberts, “Fast Yield Learning Using E-Beam Wafer Inspection” SPIE International Symposium on Microelectronics and Assembly—Singapore Nov. 27, 2000, Vol.4229, p 85–91)
Frequently, complex integrated circuit devices include a number of repetitive arrays of circuit geometry, as well as a number of peripheral circuits which typically are not repetitive. Some devices, in particular SRAMs, may include in the peripheral and storage circuitry an area comprised solely of very small circular contact holes which provide a means for connection between different levels. The accuracy and precision of the contacts are critical to device functionality and reliability.
An array of contact holes or vias in peripheral circuitry presents a particularly difficult challenge for accurate SEM inspection because of their lack of different geometric features, small size, and the large number of similar circular holes having no alignment mark or other distinctive feature near-by to precisely identify a position on the chip.
The most accurate and rapid e-beam analysis and characterization of contact holes have been made possible by the voltage contrast operating mode which may detect electrical failures and/or defects not visible by optical techniques, in both the current and underlying layers. Voltage contrast imaging shows different contrast levels depending on the surface charge of the feature under inspection.
However, a significant issue with the application of automated e-beam imaging is that the inspection tools must have a means of locating the feature under inspection which is recognizable by the system, and is in close proximity to the area under inspection. In practice, features requiring analysis may be difficult to locate if they are in random geometric areas, and are comprised of contact holes.
Existing photolithographic alignment marks used primarily for assuring correct alignment between levels and correct size of features in active circuitry are typically placed in scribe streets between individual chips, and therefore due to their remote location are not useful for SEM inspection of many critical areas on a chip.
In particular, peripheral circuitry comprised of hole patterns may not be accurately inspected by e-beam imaging because a precise location is unidentifiable. Post processing analysis of contacts is both extremely difficult and unreliable because the complex contact holes have been filled, overlaid, and otherwise obscured during processing of multilayered structures, and therefore, it is of utmost importance that the contacts be analyzed and characterized during processing.
Thus, there is a need for a new type of alignment mark specifically to identify the precise location of critical features to be inspected by e-beam imaging during wafer processing, and in particular the location of features positioned in random geometries comprised of contact holes. Further, the means for identifying a location must be distinctive enough for SEM recognition. Such an alignment mark would help shorten development time and costs for integrated circuits, and therefore, would be beneficial to the entire semiconductor industry.